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a
Dual, Precision JFET High Speed Operational Amplifier OP249
PIN CONNECTIONS 8-Lead Cerdip (Z Suffix), 8-Lead Plastic Mini-DIP (P Suffix)
OUT A 1 -IN A 2 +IN A 3 V- 4 8 V+
A B 7 OUT B -+ +- 6 -IN B
FEATURES Fast Slew Rate: 22 V/ s typ Settling Time (0.01%): 1.2 s max Offset Voltage: 300 V max High Open-Loop Gain: 1000 V/mV min Low Total Harmonic Distortion: 0.002% typ Improved Replacement for AD712, LT1057, OP215, TL072 and MC34082 Available in Die Form APPLICATIONS Output Amplifier for Fast D/As Signal Processing Instrumentation Amplifiers Fast Sample/Holds Active Filters Low Distortion Audio Amplifiers Input Buffer for A/D Converters Servo Controllers
20-Terminal LCC (RC Suffix)
OUT A NC NC NC
18 NC 17 OUT B 16 NC 15 -IN B 14 NC 9 10 11 12 13
3 NC 4 -IN A 5 NC 6 +IN A 7 NC 8
2
1 20 19
5 +IN B
NC
+IN B
NC
V+
TO-99 (J Suffix)
V+ 8 OUTA 1 A -+ B +- 6 -IN B 7 OUT B
NC = NO CONNECT
8-Lead SO (S Suffix)
+IN A V- +IN B -IN B 1 2 3 4 -A + + -B 8 7 6 5 -IN A OUT A V+ OUT B
-IN A 2
+IN A 3 4 V-
5 +IN B
GENERAL DESCRIPTION
The OP249 is a high speed, precision dual JFET op amp, similar to the popular single op amp, the OP42. The OP249 outperforms available dual amplifiers by providing superior speed with excellent dc performance. Ultrahigh open-loop gain (1 kV/mV minimum), low offset voltage and superb gain linearity, makes the OP249 the industry's first true precision, dual high speed amplifier. With a slew rate of 22 V/s typical, and a fast settling time of less than 1.2 s maximum to 0.01%, the OP249 is an ideal
choice for high speed bipolar D/A and A/D converter applications. The excellent dc performance of the OP249 allows the full accuracy of high resolution CMOS D/As to be realized. Symmetrical slew rate, even when driving large load, such as 600 or 200 pF of capacitance, and ultralow distortion, make the OP249 ideal for professional audio applications, active filters, high speed integrators, servo systems and buffer amplifiers. The OP249 provides significant performance upgrades to the TL072, AD712, OP215, MC34082 and the LT1057.
0.010 TA = +25 C VS = 15V VO = 10V p-p RL = 10k AV = +1
870ns
100 90
100 90
10 0%
10 0%
10mV
500ns
5V
1s
0.001 20
100
1k
10k 20k
Figure 1. Fast Settling (0.01%)
Figure 2. Low Distortion AV = +1, RL = 10 k
Figure 3. Excellent Output Drive, RL = 600
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
NC
V-
OP249-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V =
S
15 V, TA = +25 C, unless otherwise noted)
OP249A Min Typ Max 0.2 0.5 0.8 OP249E Min Typ Max 0.1 0.3 0.6 Min OP249F Typ Max 0.2 0.7 1.0 Units mV mV V/Month pA pA V V V dB V/V V/mV V V V mA mA mA mA V/s MHz s Degrees pF V p-p nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz V
Parameter Offset Voltage Long Term Offset Voltage Offset Stability Input Bias Current Input Offset Current Input Voltage Range
Symbol Conditions VOS VOS IB IOS IVR (Note 1) VCM = 0 V, TJ = +25C VCM = 0 V, TJ = +25C (Note 2)
11
1.5 30 75 6 25 +12.5
11
1.5 20 50 4 15 +12.5
11 80 500 12.0 20
1.5 30 75 6 25 +12.5 -12.5 90 12 50 1200 +12.5 -12.5 +36
Common-Mode Rejection Power-Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing
CMR PSRR AVO VO
Short-Circuit Current Limit
ISC
Supply Current Slew Rate Gain-Bandwidth Product Settling Time Phase Margin Differential Input Impedance Open-Loop Output Resistance Voltage Noise Voltage Noise Density
ISY SR GBW tS 0 ZIN RO en p-p en
Current Noise Density Voltage Supply Range
in VS
-12.5 80 90 VCM = 11 V 12 31.6 VS = 4.5 V to 18 V VO = 10 V, RL = 2 k 1000 1400 RL = 2 k +12.5 12.0 -12.5 Output Shorted to +36 Ground 20 50 -33 No Load, VO = 0 V 5.6 7.0 22 RL = 2 k, CL = 50 pF 18 (Note 4) 3.5 4.7 10 V Step 0.01%3 0.9 1.2 0 dB Gain 55 1012 6 35 0.1 Hz to 10 Hz 2 fO = 10 Hz 75 26 fO = 100 Hz 17 fO = 1 kHz 16 fO = 10 kHz fO = 1 kHz 0.003 4.5 15 18
-12.5 86 95 9 31.6 1000 1400 +12.5 12.0 -12.5 +36 20 50 -33 5.6 7.0 18 22 3.5 4.7 0.9 1.2 55 1012 6 35 2 75 26 17 16 0.003 4.5 15 18
18 3.5
4.5
50 -33 5.6 7.0 22 4.7 0.9 1.2 55 1012 6 35 2 75 26 17 16 0.003 15 18
NOTES 1 Long-term offset voltage is guaranteed by a 1000 HR life test performed on three independent wafer lots at +125 C with LTPD of three. 2 Guaranteed by CMR test. 3 Settling time is sample tested. 4 Guaranteed by design. Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (@ V =
S
15 V, TA = +25 C, unless otherwise noted)
Min OP249G Typ 0.4 40 10 +12.5 -12.0 90 12 1100 +12.5 -12.5 +36 -33 5.6 22 4.7 0.9 55 1012 6 Max 0.2 75 25 Units mV pA pA V V V dB V/V V/mV V V V mA mA mA mA V/s MHz s Degree pF
Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range
Symbol VOS IB IOS IVR
Conditions VCM = 0 V, TJ = +25C VCM = 0 V, TJ = +25C (Note 1) VCM = 11 V VS = 4.5 V to 18 V VO = 10 V; RL = 2 k RL = 2 k
11 76 500 12.0 20
Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing
CMR PSRR AVO VO
50
Short-Circuit Current Limit
ISC
Output Shorted to Ground
50 7.0
Supply Current Slew Rate Gain Bandwidth Product Settling Time Phase Margin Differential Input Impedance
ISY SR GBW tS 0 ZIN
No Load; VO = 0 V RL = 2 k, CL = 50 pF (Note 2) 10 V Step 0.01% 0 dB Gain
18
1.2
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OP249
Parameter Open Loop Output Resistance Voltage Noise Voltage Noise Density Symbol RO en p-p en Conditions 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz fO = 1 kHz Min OP249G Typ 35 2 75 26 17 16 0.003 15 Max Units V p-p nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz V
Current Noise Density Voltage Supply Range
NOTES 1 Guaranteed by CMR test. 2 Guaranteed by design.
in VS
4.5
18
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS A grade unless otherwise noted)
Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Voltage Range Symbol Conditions VOS TCVOS IB IOS IVR OP249A Min Typ Max 0.12 1.0
(@ VS =
15 V, -40 C TA +85 C for E/F grades, and -55 C TA +125 C for
OP249E Min Typ Max 0.1 0.5 OP249F Typ Max 0.5 1.1
Min
Units mV V/C nA nA V V V dB V/V V/mV V V V mA mA
(Note 1) (Note 1) (Note 2)
11
1 5 4 20 0.04 4 +12.5 -12.5 110 5 50 1400 +12.5 -12.5
11 86 750 12.0 18
1 3 0.25 3.0 0.01 0.7 +12.5 -12.5 100 5 50 1400 +12.5 -12.5
11 80 250 12.0 18
2.2 6 0.3 4.0 0.02 1.2 +12.5 -12.5 90 7 100 1200 +12.5 -12.5
Common-Mode Rejection Power-Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing
CMR PSRR AVO VO
76 VCM = 11 V VS = 4.5 V to 18 V RL = 2 k; VO = 10 V 500 RL = 2 k 12.0 Output Shorted to Ground No Load, VO = 0 V 10
Short-Circuit Current Limit Supply Current
ISC ISY
5.6
60 7.0
5.6
60 7.0
5.6
60 7.0
NOTES 1 TJ = +85C for E/F Grades; T J = +125C for A Grade. 2 Guaranteed by CMR test. Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Voltage Range Symbol VOS TCVOS IB IOS IVR
(@ VS =
15 V, -40 C TA +85 C for unless otherwise noted)
Min OP249G Typ 1.0 6 0.5 0.04 +12.5 -12.5 95 10 1200 +12.5 -12.5 Max 3.6 25 4.5 1.5 Units mV V/C nA nA V V V dB V/V V/mV V V V mA mA
Conditions
(Note 1) (Note 1) (Note 2) VCM = 11 V VS = 4.5 V to 18 V RL = 2 k; VO = 10 V RL = 2 k
11 76 250 12.0 18
Common-Mode Rejection Power-Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing
CMR PSRR AVO VO
100
Short-Circuit Current Limit Supply Current
NOTES 1 TJ = +85C . 2 Guaranteed by CMR test.
ISC ISY
Output Shorted to Ground No Load, VO = 0 V
5.6
60 7.0
Specifications subject to change without notice.
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OP249
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . 36 V Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . -65C to +175C Operating Temperature Range OP249A (J, Z, RC) . . . . . . . . . . . . . . . . . . -55C to +125C OP249E, F (J, Z) . . . . . . . . . . . . . . . . . . . . -40C to +85C OP249G (P, S) . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature OP249 (J, Z, RC) . . . . . . . . . . . . . . . . . . . -65C to +175C OP249 (P, S) . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering, 60 sec) . . . . . . +300C
Package Type TO-99 (J) 8-Lead Hermetic DIP (Z) 8-Lead Plastic DIP (P) 20-Terminal LCC (RC) 8-Lead SO (S)
3 JA
JC
Units C/W C/W C/W C/W C/W
145 134 96 88 150
16 12 37 33 41
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage. 3 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for TO, cerdip, P-DIP, and LCC packages; JA is specified for device soldered to printed circuit board for SO package.
ORDERING GUIDE1
Model OP249AZ2 OP249ARC/883 OP249EJ OP249FZ OP249GP OP249GS3 OP249GS-REEL OP249GS-REEL7
Temperature Range -55C to +125C -55C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Descriptions2 8-Lead Cerdip 20-Terminal LCC TO-99 H-08A 8-Lead Cerdip 8-Lead Plastic DIP 8-Lead SO 8-Lead SO 8-Lead SO
Package Options Q-8 E-20A H-08A Q-8 N-8 SO-8 SO-8 SO-8
NOTES 1 Burn-in is available on commercial and industrial temperature range parts in cerdip, plastic DIP, and TO-can packages. 2 For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory for 883 data sheet. 3 For availability and burn-in information on SO and PLCC packages, contact your local sales office.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP249 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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REV. C
OP249
DICE CHARACTERISTICS
V+
OUT (A) -IN (A)
OUT (B) -IN (B)
+IN (A)
+IN (B)
V-
DIE SIZE 0.072 0.112 inch, 8,064 sq. mils (1.83 2.84 mm, 5.2 sq. mm)
WAFER TEST LIMITS (@ V =
S
15 V, TJ = +25 C unless otherwise noted)
Symbol VOS TCVOS IB IOS IVR CMR PSRR AVO VO ISC ISY SR Conditions -40C TJ 85C VCM = 0 V VCM = 0 V (Note 1) VCM = 11 V VS = 4.5 V to 18 V RL = 2 k RL = 2 k Output Shorted to Ground No Load; VO = 0 V RL = 2 k, CL = 50 pF OP249GBC Limits 0.5 6.0 225 75 11 76 100 250 12.0 20/ 60 7.0 16.5 Units mV max V/C max pA max pA max V min dB min V/V max V/mV min V min mA min/max mA max V/s min
Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Power Supply Rejection Ratio Large-Signal Voltage Gain Output Voltage Swing Short-Circuit Current Limit Supply Current Slew Rate
NOTES 1 Guaranteed by CMR test. Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
REV. C
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OP249-Typical Performance Characteristics
120 100
OPEN-LOOP GAIN - dB
65
TA = +25 C VS = 15V RL = 2k
10
GAIN BANDWIDTH PRODUCT - MHz
140
COMMON-MODE REJECTION - dB
VS = 60
15V
120 100 80 60 40 20 0 100
TA = +25 C VS = 15V
80 60 40
0
PHASE - C
PHASE MARGIN - C
8 m
GAIN
45 90
55 GBW 50
6
PHASE 20 0 -20 1k 10k
m = 55 135 180 225 100M
4
100k 1M 10M FREQUENCY - Hz
45 -75
-50 -25 0 25 50 75 TEMPERATURE - C
2 100 125
1k
10k 100k FREQUENCY - Hz
1M
10M
Figure 4. Open-Loop Gain, Phase vs. Frequency
Figure 5. Gain Bandwidth Product, Phase Margin vs. Temperature
Figure 6. Common-Mode Rejection vs. Frequency
120
28
TA = +25 C VS = 15V SLEW RATE - V/ s
28
POWER SUPPLY REJECTION - dB
100
26
VS = 15V RL = 2k CL = 50pF
SLEW RATE - V/ s
26
TA = +25 C VS = 15V RL = 2k
80 +PSRR 60 -PSRR 40
24 -SR 22 +SR
24
22
20
20
20 0 10
18 16 -75
18 16
100
10k 100k 1k FREQUENCY - Hz
1M
-50 -25 0 25 50 75 TEMPERATURE - C
100 125
0
0.2 0.4 0.6 0.8 1.0 DIFFERENTIAL INPUT VOLTAGE - Volts
Figure 7. Power Supply Rejection vs. Frequency
Figure 8. Slew Rate vs. Temperature
Figure 9. Slew Rate vs. Differential Input Voltage
35 TA = +25 C VS = 15V
10
VOLTAGE NOISE DENSITY - nV Hz
100
8 OUTPUT STEP SIZE - Volts 6 4 2 0 -2 -4 -6 -8
30
TA = +25 C VS = 15V AVCL = +1
0.1%
80
TA = +25 C VS = 15V
SLEW RATE - V/ s
25
NEGATIVE
0.01%
60
20
POSITIVE
0.01%
40
15
0.1%
20
10 5
-10
0 100 200 300 400 CAPACITIVE LOAD - pF 500
0
0
200
400 600 800 SETTLING TIME - ns
1000
0
100 1k FREQUENCY - Hz
10k
Figure 10. Slew Rate vs. Capacitive Load
Figure 11. Settling Time vs. Step Size
Figure 12. Voltage Noise Density vs. Frequency
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OP249
0.010 TA = +25 C VS = 15V VO = 10V p-p RL = 10k AV = +1
0.010 TA = +25 C VS = 15V VO = 10V p-p RL = 2k AV = +1
0.010
TA = +25 C VS = 15V VO = 10V p-p RL = 600 AV = +1
0.001 20
100
1k
10k 20k
0.001 20
100
1k
10k 20k
0.001 20
100
1k
10k 20k
Figure 13. Distortion vs. Frequency
Figure 14. Distortion vs. Frequency
Figure 15. Distortion vs. Frequency
0.10
TA = +25 C VS = 15V VO = 10V p-p RL = 10k AV = +1
0.10
TA = +25 C VS = 15V VO = 10V p-p RL = 2k AV = +10
0.10 TA = +25 C VS = 15V VO = 10V p-p RL = 600 AV = +10
0.010 20
100
1k
10k 20k
0.010 20
100
1k
10k 20k
0.010 20
100
1k
10k 20k
Figure 16. Distortion vs. Frequency
Figure 17. Distortion vs. Frequency
Figure 18. Distortion vs. Frequency
60
50
500mV
1s
CLOSED-LOOP GAIN - dB
50 AVCL = +100 40 30 AVCL = +10 20 10 0 -10 -20 1k AVCL = +5
TA = +25 C VS = 15V
40
TA = +25 C VS = 15V
IMPEDANCE -
+1 V -1 V
30
AVCL = +10
AVCL = +1
20
AVCL = +100
BANDWIDTH (0.1Hz TO 10 Hz) TA = +25 C VS = 15V
AVCL = +1
10
10k
100k 1M 10M FREQUENCY - Hz
100M
0 100
1k
10k 100k FREQUENCY - Hz
1M
10M
Figure 19. Low Frequency Noise
Figure 20. Closed-Loop Gain vs. Frequency
Figure 21. Closed-Loop Output Impedance vs. Frequency
REV. C
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OP249
30 MAXIMUM OUTPUT SWING - Volts 25
80 70
OVERSHOOT - %
MAXIMUM OUTPUT SWING - Volts
TA = +25 C VS = 15V AVCL = +1 RL = 10k
90 VS = 15V RL = 2k VIN = 100mV p-p AVCL = +1 NEGATIVE EDGE AVCL = +1 POSITIVE EDGE
16 14 12 +VOHM = |-VOHM | 10 8 6 4 2 0 100 TA = +25 C VS = 15V
20
60 50 40 30 20
15
10
5
10
0 1k
AVCL = +5 0 100 200 300 400 LOAD CAPACITANCE - pF 500
1k LOAD RESISTANCE - 10k
0
10k 100k 1M FREQUENCY - Hz 10M
Figure 22. Maximum Output Swing vs. Frequency
Figure 23. Small Overshoot vs. Load Capacitance
Figure 24. Maximum Output Voltage vs. Load Resistance
20
6.0 TA = +25 C RL = 2k
SUPPLY CURRENT - mA
6.0
VS = 15V NO LOAD
OUTPUT VOLTGE SWING - Volts
15 10 5 0 -5 -10 -15 -20 0
5.8
SUPPLY CURRENT - mA
5.8 TA = +25 C 5.6 TA = +125 C 5.4 TA = -55 C 5.2
5.6
5.4
5 10 15 SUPPLY VOLTAGE - Volts
20
5.2 -75 -50 -25 0 25 50 75 TEMPERATURE - C
100 125
5.0
0
5 10 15 SUPPLY VOLTAGE - Volts
20
Figure 25. Output Voltage Swing vs. Supply Voltage
Figure 26. Supply Current vs. Temperature
Figure 27. Supply Current vs. Supply Voltage
360 320 280 240
UNITS
180 TA = +25 C VS = 15V 350 OP249 (700 OP AMPS) 160 140 120 TA = +25 C VS = 15V 415 OP249 (830 OP AMPS)
270 240 210 180
UNITS
VS = 15V -40 C TO +85 C (700 OP AMPS)
UNITS
200 160 120 80 40 0 -1k -200 200 600 1k -600 -800 -400 0 400 800 VOS - V
100 80 60 40 20 0 -1k -200 200 600 1k -600 -800 -400 0 400 800 VOS - V
150 120 90 60 30 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V/ C
Figure 28. VOS Distribution (J Package)
Figure 29. VOS Distribution (P Package)
Figure 30. TCVOS Distribution (J Package)
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OP249
300 270 240 210 180
UNITS
50
INPUT BIAS CURRENT - pA
VS = 15V -40 C TO +85 C (830 OP AMPS)
OFFSET VOLTAGE - V
10k
VS = 15V
VS = 15V VCM = 0V 1k
40
30
150 120 90 60 30 0 0 2 4 6 8 10 12 14 16 18 20 22 24 V/ C
100
20
10
10
0
0
2 4 3 5 1 TIME AFTER POWER APPLIED - Minutes
1 -75 -50 -25
0
25
50
75
100 125
TEMPERATURE - C
Figure 31. TCVOS Distribution (P Package)
Figure 32. Offset Voltage Warm-Up Drift
Figure 33. Input Bias Current vs. Temperature
104
TA = +25 C VS = 15V
INPUT BIAS CURRENT - pA
50 TA = +25 C VS = 15V 40
80
BIAS CURRENT - pA
103
INPUT OFFSET CURRENT - pA
TA = +25 C VCM = 0V 60
30
102
40
20
101
20
10
100 -15
-10
-5
0
5
10
15
0
0
COMMON-MODE VOLTAGE - Volts
2 4 6 8 10 TIME AFTER POWER APPLIED - Minutes
0 0 25 50 75 -75 -50 -25 TEMPERATURE - C
100 125
Figure 34. Bias Current vs. Common-Mode Voltage
Figure 36. Bias Current Warm-Up Drift
Figure 36. Input Offset Current vs. Temperature
SHORT-CIRCUIT OUTPUT CURRENT - mA
80 VS =
OPEN-LOOP GAIN - V/mV
80 VS = 15V
15V
60
60 SOURCE 40
RL = 10k 40 RL = 2k 20
SINK
20
0 0 25 50 75 -75 -50 -25 TEMPERATURE - C
100 125
0 0 25 50 75 -75 -50 -25 TEMPERATURE - C
100 125
Figure 37. Open-Loop Gain vs. Temperature
Figure 38. Short-Circuit Output Current vs. Junction Temperature
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OP249
V+ +IN VOUT
APPLICATIONS INFORMATION
-IN
The OP249 represents a reliable JFET amplifier design, featuring an excellent combination of dc precision and high speed. A rugged output stage provides the ability to drive a 600 load and still maintain a clean ac response. The OP249 features a large signal response that is more linear and symmetric than previously available JFET input amplifiers--compare the OP249's large-signal response, as illustrated in Figure 41, to other industry standard dual JFET amplifiers. Typically, JFET amplifier's stewing performance is simply specified as just a number of volts/s. There is no discussion on the quality, i e., linearity, symmetry, etc., of the stewing response.
V-
Figure 39. Simplified Schematic (1/2 OP249)
1/2 OP249 +3V 5k
+18V
A) OP249
1/2 OP249 +3V -18V 5k
Figure 40. Burn-In Circuit
B) LT1057
C) AD712
Figure 41. Large-Signal Transient Response, AV = +1, VIN = 20 V p-p, ZL = 2 k//200 pF, VS = 15 V
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OP249
The OP249 was carefully designed to provide symmetrically matched slew characteristics in both the negative and positive directions, even when driving a large output load. An amplifier's slewing limitation determines the maximum frequency at which a sinusoidal output can be obtained without significant distortion. It is, however, important to note that the nonsymmetric stewing typical of previously available JFET amplifiers adds a higher series of harmonic energy content to the resulting response--and an additional dc output component. Examples of potential problems of nonsymmetric slewing behavior could be in audio amplifier applications, where a natural low distortion sound quality is desired, and in servo or signal processing systems where a net dc offset cannot be tolerated. The linear and symmetric stewing feature of the OP249 makes it an ideal choice for applications that will exceed the full-power bandwidth range of the amplifier.
VERTICAL 50 V/DIV INPUT VARIATION
HORIZONTAL 5V/DIV OUTPUT CHARGE
Figure 43. Open-Loop Gain Linearity. Variation in OpenLoop Gain Results in Errors in High Closed-Loop Gain Circuits. RL = 600 , VS = 15 V
R4 +V VIN R5 50k R1 200k R2 31 -V 1/2 OP249 VOUT R3
VOS ADJUST RANGE =
V R2 R1
Figure 44. Offset Adjust for Inverting Amplifier Configuration
+V
Figure 42. Small-Signal Transient Response, AV = +1, ZL = 2 k 100 pF, No Compensation, VS = 15 V
R5 R3 50k R1 200k R2 33 -V VIN VOS ADJUST RANGE = GAIN = VOUT VIN =1+ V R4 1/2 OP249 VOUT
As with most JFET-input amplifiers, the output of the OP249 may undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion will not damage the amplifier, nor will it cause an internal latch-up condition. Supply decoupling should be used to overcome inductance and resistance associated with supply lines to the amplifier. A 0.1 F and a 10 F capacitor should be placed between each supply pin and ground.
OPEN-LOOP GAIN LINEARITY
R2 R1
R5 R4 + R2
1 + R5 IF R2 << R4 R4
Figure 45. Offset Adjust for Noninverting Amplifier Configuration
The OP249 has both an extremely high open-loop gain of 1 kV/mV minimum and constant gain linearity. This feature of the OP249 enhances its dc precision, and provides superb accuracy in high closed-loop gain applications. Figure 43 illustrates the typical open-loop gain linearity--high gain accuracy is assured, even when driving a 600 load.
OFFSET VOLTAGE ADJUSTMENT
The inherent low offset voltage of the OP249 will make offset adjustments unnecessary in most applications. However, where a lower offset error is required, balancing can be performed with simple external circuitry, as illustrated in Figures 44 and 45.
In Figure 44, the offset adjustment is made by supplying a small voltage at the noninverting input of the amplifier. Resistors R1 and R2 attenuates the pot voltage, providing a 2.5 mV (with VS = 15 V) adjustment range, referred to the input. Figure 45 illustrates offset adjust for the noninverting amplifier configuration, also providing a 2.5 mV adjustment range. As indicated in the equations in Figure 45, if R4 is not much greater than R2, there will be a resulting closed-loop gain error that must be accounted for.
REV. C
-11-
OP249
SETTLING TIME DAC OUTPUT AMPLIFIER
Settling time is the time between when the input signal begins to change and when the output permanently enters a prescribed error band. The error bands on the output are 5 mV and 0.5 mV, respectively, for 0.1% and 0.01% accuracy. Figure 46 illustrates the OP249's typical settling time of 870 ns. Moreover, problems in settling response, such as thermal tails and long-term ringing are nonexistent.
Unity-gain stability, a low offset voltage of 300 V typical, and a fast settling time of 870 ns to 0.01%, makes the OP249 an ideal amplifier for fast digital-to-analog converters. For CMOS DAC applications, the low offset voltage of the OP249 results in excellent linearity performance. CMOS DACs, such as the PM-7545, will typically have a code-dependent output resistance variation between 11 k and 33 k. The change in output resistance, in conjunction with the 11 k feedback resistor, will result in a noise gain change. This causes variations in the offset error, increasing linearity errors. The OP249 features low offset voltage error, minimizing this effect and maintaining 12-bit linearity performance over the full-scale range of the converter. Since the DAC's output capacitance appears at the operational amplifiers inputs, it is essential that the amplifier is adequately compensated. Compensation will increase the phase margin, and ensure an optimal overall settling response. The required lead compensation is achieved with Capacitor C in Figure 47.
870ns
100 90
10 0%
10mV
500ns
Figure 46. Settling Characteristics of the OP249 to 0.01%
VDD 0.1 F 75 C 33pF REFERENCE OR VIN OUT1 VREF 500 PM7545 1/2 OP249 0.1 F -15V VOUT DB11 - DB0 AGND 12 DATA INPUT +15V
a. Unipolar Operation
R4 20k 1% VDD 0.1 F 75 C 33pF OUT1 VREF PM7545 AGND DGND DB11 - DB0 12 DATA INPUT VDD RFB +15V 0.1 F R3 10k 1% 1/2 OP249 0.1 F -15V VOUT R5 10k 1%
REFERENCE OR VIN
500
1/2 OP249
b. Bipolar Operation
Figure 47. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance
-12-
REV. C
OP249
A B
C = 5pF RESPONSE IS GROSSLY UNDERDAMPED, AND EXHIBITS RINGING
C = 15pF FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE OF SLIGHT PEAKING IN RESPONSE
Figure 48. Effect of Altering Compensation from Circuit in Figure 47a--PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation. Critically Damped Response Will Be Obtained with C 33 pF
Figure 48 illustrates the effect of altering the compensation on the output response of the circuit in Figure 48a. Compensation is required to address the combined effect of the DAC's output capacitance, the op amp's input capacitance and any stray capacitance. Slight adjustments to the compensation capacitor may be required to optimize settling response for any given application . The settling time of the combination of the current output DAC and the op amp can be approximated by:
tS TOTAL = (tS DAC )2 +(tS AMP )2
+15V
0.1 F
1/2 OP249 0.1 F * -15V 300pF +15V 1.5k TTL INPUT 1N4148 1.8k +15V 0.1 F * *NOTE: DECOUPLE CLOSE TOGETHER ON GROUND PLANEWITH SHORT LEAD LENGTHS VREF 220 0.01 F 0.47 F 2N2907 1k 2N3904 10 F 1k
7A13 PLUG-IN
7A13 PLUG-IN
IOUT =
|VREF | 1k
The actual overall settling time is affected by the noise gain of the amplifier, the applied compensation, and the equivalent input capacitance at the amplifier's input.
DISCUSSION ON DRIVING A/D CONVERTERS
Settling characteristics of operational amplifiers also include an amplifier's ability to recover, i.e., settle, from a transient current output load condition. An example of this includes an op amp driving the input from a SAR type A/D converter. Although the comparison point of the converter is usually diode clamped, the input swing of plus-and-minus a diode drop still gives rise to a significant modulation of input current. If the closed-loop output impedance is low enough and bandwidth of the amplifier is sufficiently large, the output will settle before the converter makes a comparison decision which will prevent linearity errors or missing codes. Figure 49 shows a settling measurement circuit for evaluating recovery from an output current transient. An output disturbing current generator provides the transient change in output load current of 1 mA. As seen in Figure 50, the OP249 has extremely fast recovery of 274 ns (to 0.01%), for a 1 mA load transient. The performance makes it an ideal amplifier for data acquisition systems.
Figure 49. Transient Output Impedance Test Fixture
The combination of high speed and excellent dc performance of the OP249 makes it an ideal amplifier for 12-bit data acquisition systems. Examining the circuit in Figure 51, one amplifier in the OP249 provides a stable -5 V reference voltage for the VREF input of the ADC912. The other amplifier in the OP249 performs high speed buffering of the A/D's input. Examining the worst case transient voltage error (Figure 52) at the Analog In node of the A/D converter: the OP249 recovers in less than 100 ns. The fast recovery is due to both the OP249's wide bandwidth and low dc output impedance.
REV. C
-13-
OP249
Figure 50. OP249's Transient Recovery Time from a 1 mA Load Transient to 0.01%
Figure 52. Worst Case Transient Voltage, at Analog In, Occurs at the Half-Scale Point of the A/D. OP249 Buffers the A/D Input from Figure 51, and Recovers in Less than 100 ns.
+15V 0.1 F
+5V 10 F||0.1 F
-15V 10 F||0.1 F
ANALOG INPUT
1/2 OP249 0.1 F ADC912 RD CLK IN BUSY CS
+15V 0.1 F
-15V
ANALOG IN VREFIN
AGND DGND HBEN 0.1 F
IN REF02 OUT GND 1/2 OP249 10 -5V 10 F||0.1 F
Figure 51. OP249 Dual Amplifiers Provide Both Stable -5 V Reference Input, and Buffers Input to ADC912
-14-
REV. C
OP249
OP249 SPICE MACRO-MODEL
Figures 53 and Table I show the node and net list for a SPICE macromodel of the OP249 The model is a simplified version of the actual device and simulates important dc parameters such as VOS, IOS, IB, AVO, CMR, VO and ISY. AC parameters such as slew rate, gain and phase response and CMR change with frequency are also simulated by the model.
99 V2 I1 4 2 IN- R1 IOS CIN 3 R2 1 IN+ D2 5 C2 R3 50 R4 6 10 V3 G2 EOS J1 J2 7 8 D1 G1
The model uses typical parameters for the OP249. The poles and zeros in the model were determined from the actual open and closed-loop gain and phase response of the OP249. In this way the model presents an accurate ac representation of the actual device. The model assumes an ambient temperature of 25C.
C5 G5 R5 C3 G3 R7 12 15
R11
L1
R9 14 9 R10 R6 C4 G4 R8 13 C6 16 G6
R12
R13
R14
L2
99 L3 21
G7
R15
C9
G9
R17
C11
G11
R19
C13
G13
R21 17 18 19 20 R22 G8 R16 C10 G10 R18 C12 G12 R20 C14 G14 22 L4 50
99
D5 G15 R23 C15 R25 D3 24 25
D6 V4 +-
G19 R27
L5 23 D4 26 27 28 G20 D7 50 G17 G18 D8 V5 -+ R28 29
30 VOUT
G16
R24
C16
R26
Figure 53. OP249 Macro-Model
REV. C
-15-
OP249
Table I. SPICE Net List
OP249 MACRO-MODEL * subckt OP249 1 2 30 99 50 * INPUT STAGE & POLE AT 100MHz * r1 2 3 5E11 r2 1 3 5E11 r3 5 50 652.3 r4 6 50 652.3 cin 1 2 5E-12 c2 5 6 1.22E-12 i1 99 4 1E-3 ios 1 2 3.1E-12 eos 7 1 poly(1) 20 24 150E-6 1 j1 5 2 4 jx j2 6 7 4 jx * * SECOND STAGE & POLE AT 12.2Hz * r5 9 99 326.1E6 r6 9 50 326.1E6 c3 9 99 40E-12 c4 9 50 40E-12 g1 99 9 poly(1) 5 6 4.25E-3 1.533E-3 g2 9 50 poly(1) 6 5 4.25E-3 1.533E-3 v2 99 8 2.9 v3 10 50 2.9 d1 9 8 dx d2 10 9 dx * * POLE-ZERO PAIR AT 2MHz/4.0MHz * r7 11 99 1E6 r8 11 50 1E6 r9 11 12 1E6 r10 11 13 1E6 c5 12 99 37.79E-15 c6 13 50 37.79E-15 g3 99 11 9 24 1E-6 g4 11 50 24 9 1E-6 * * ZERO-POLE PAIR AT 4MHz/8MHz * r11 99 15 IE6 r12 14 15 1E6 r13 14 16 1E6 r14 50 16 1E6 I1 99 15 19.89E-3 I2 50 16 19.89E-3 g5 99 14 11 24 1E-6 g6 14 50 24 11 1E-6 * * POLE AT 20MHz * r15 17 99 1E6 r16 17 50 1E6 c9 17 99 7.96E-15 c10 17 50 7.96E-15 g7 99 17 14 24 1E-6 g8 17 50 24 14 1E-6 * * POLE AT 50MHz * r17 18 99 1E6 r18 18 50 1E6 c11 18 99 3.18E-15 c12 18 50 3.18E-15 g9 99 18 17 24 1E-6 g10 18 50 24 17 1E-6 * * POLE AT 50MHz * r19 19 99 1E6 r20 19 50 1E6 c13 19 99 3.18E-15 c14 19 50 3.18E-15 g11 99 19 18 24 1E-6 g12 19 50 24 18 1E-6 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 60kHZ * r21 20 21 1E6 r22 20 22 1E6 I3 21 99 2.65 I4 22 50 2.65 g13 99 20 3 24 1.78E-11 g14 20 50 24 3 1.78E-11 * * POLE AT 50MHZ * r23 23 99 1E6 r24 23 50 1E6 c15 23 99 3.18E-15 c16 23 50 3.18E-15 g15 99 23 19 24 1E-6 g16 23 50 24 19 1E-6 * * OUTPUT STAGE * r25 24 99 135E3 r26 24 50 135E3 r27 29 99 70 r28 29 50 70 I5 29 30 4E-7 g17 27 50 23 29 14.3E-3 g18 28 50 29 23 14.3E-3 g19 29 99 99 23 14.3E-3 g20 50 29 23 50 14.3E-3 v4 25 29 .4 v5 29 26 .4 d3 23 25 dx d4 26 23 dx d5 99 27 dx d6 99 28 dx d7 50 27 dy d8 50 28 dy * MODELS USED * * model jx PJF(BETA=1.175E-3 VTO=-2.000 IS=21E-12) * model dx D(IS=1E-15) * model dy D(IS=1E-15 BV=50) * ends OP249
**PSpice is a registered trademark of MicroSim Corporation. ** HSPICE is a tradename of Meta-Software, Inc.
-16-
REV. C
OP249
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Terminal Leadless Chip Carrier (E-20A)
0.200 (5.08) BSC 0.100 (2.54) BSC
3 4 1
8-Lead Metal Can (TO-99) (H-08A)
REFERENCE PLANE 0.750 (19.05) 0.500 (12.70) 0.250 (6.35) MIN 0.050 (1.27) MAX 0.100 (2.54) BSC 5 0.335 (8.51) 0.305 (7.75) 0.370 (9.40) 0.335 (8.51) 4 0.200 (5.08) BSC 3 2 0.019 (0.48) 0.016 (0.41) 0.021 (0.53) 0.016 (0.41) BASE & SEATING PLANE 0.100 (2.54) BSC 1 0.034 (0.86) 0.027 (0.69) 45 BSC 8 6 7 0.045 (1.14) 0.027 (0.69) 0.160 (4.06) 0.110 (2.79)
0.358 (9.09) 0.342 (8.69) SQ
0.100 (2.54) 0.064 (1.63) 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF
0.075 (1.91) REF
19 18 20
0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC
0.185 (4.70) 0.165 (4.19)
TOP VIEW
0.358 (9.09) MAX SQ
BOTTOM VIEW
14 13 8 9
0.088 (2.24) 0.054 (1.37)
0.055 (1.40) 0.045 (1.14)
45 TYP 0.150 (3.81) BSC
0.040 (1.02) MAX 0.045 (1.14) 0.010 (0.25)
8-Lead Plastic DIP (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
8-Lead Narrow Body (SOIC) (SO-8)
0.1968 (5.00) 0.1890 (4.80)
1
4
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.1574 (4.00) 0.1497 (3.80)
8 1
5 4
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.210 (5.33) MAX
0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) SEATING PLANE 0.014 (0.356) (2.54) 0.045 (1.15) BSC
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.015 (0.381) 0.008 (0.204)
0.0500 0.0192 (0.49) SEATING (1.27) 0.0098 (0.25) PLANE BSC 0.0138 (0.35) 0.0075 (0.19)
8 0 0.0500 (1.27) 0.0160 (0.41)
8-Lead Cerdip (Q-8)
0.005 (0.13) MIN
8
0.055 (1.4) MAX
5
1
4
PIN 1 0.405 (10.29) MAX 0.200 (5.08) MAX
0.060 (1.52) 0.015 (0.38)
0.320 (8.13) 0.290 (7.37)
0.150 (3.81) 0.200 (5.08) MIN 0.125 (3.18) 0.023 (0.58) 0.100 0.070 (1.78) SEATING PLANE 0.014 (0.36) (2.54) 0.030 (0.76) BSC
15 0
0.015 (0.38) 0.008 (0.20)
REV. C
-17-
PRINTED IN U.S.A.
0.310 (7.87) 0.220 (5.59)
C1976a-0-6/98

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